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    ICCAD
    2005
    IEEE
    127views Hardware» more  ICCAD 2005»
    Flip-flop insertion with shifted-phase clocks for FPGA power reduction
    14 years 2 months ago
    Flip-flop insertion with shifted-phase clocks for FPGA power reduction
    Download  www.power-reduction.com
    — Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
    Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
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    CCECE
    2006
    IEEE
    244views Electrical And Computer Engi...» more  CCECE 2006»
    QOS Driven Network-on-Chip Design for Real Time Systems
    13 years 11 months ago
    QOS Driven Network-on-Chip Design for Real Time Systems
    Download  www.cvsi.fau.edu
    Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
    Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
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