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» Synchronous Transfer Architecture (STA)
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MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 3 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
SIGMETRICS
2009
ACM
157views Hardware» more  SIGMETRICS 2009»
13 years 11 months ago
Delay tolerant bulk data transfers on the internet
Many emerging scientific and industrial applications require transferring multiple Tbytes of data on a daily basis. Examples include pushing scientific data from particle accele...
Nikolaos Laoutaris, Georgios Smaragdakis, Pablo Ro...
DSN
2009
IEEE
13 years 11 months ago
Fast memory state synchronization for virtualization-based fault tolerance
Virtualization provides the possibility of whole machine migration and thus enables a new form of fault tolerance that is completely transparent to applications and operating syst...
Maohua Lu, Tzi-cker Chiueh
INFOCOM
2002
IEEE
13 years 9 months ago
Fast PDA Synchronization Using Characteristic Polynomial Interpolation
—Modern Personal Digital Assistant (PDA) architectures often utilize a wholesale data transfer protocol known as “slow sync” for synchronizing PDAs with Personal Computers (P...
Ari Trachtenberg, David Starobinski, Sachin Agarwa...
CASES
2007
ACM
13 years 8 months ago
Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Efficient utilization of...
Chengmo Yang, Alex Orailoglu