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TVLSI
2010
13 years 1 days ago
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
Zhiyi Yu, Bevan M. Baas
DATE
2005
IEEE
165views Hardware» more  DATE 2005»
13 years 11 months ago
Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture
With the advent of multi-processor systems on a chip, the interest for message passing libraries has revived. Message passing helps in mastering the design complexity of parallel ...
Francesco Poletti, Antonio Poggiali, Paul Marchal
SPIESR
1996
118views Database» more  SPIESR 1996»
13 years 6 months ago
Performances of Multiprocessor Multidisk Architectures for Continuous Media Storage
Multimedia interfaces increase the need for large image databases, capable of storing and reading streams of data with strict synchronicity and isochronicity requirements. In orde...
Benoit A. Gennart, Vincent Messerli, Roger D. Hers...
POS
1987
Springer
13 years 8 months ago
Realisation of a Dynamically Grouped Object-Oriented Virtual Memory Hierarchy
Conventional paging systems do not perform well with large object-oriented environments (such as Smalltalk-801 [GR83]) due to the fine granularity of objects and the persistence o...
Ifor Williams, Mario Wolczko, T. P. Hopkins
DAC
2006
ACM
14 years 6 months ago
Efficient simulation of critical synchronous dataflow graphs
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko,...