3 search results - page 1 / 1 » Synthesis and Optimization of Interface Hardware between IP'... |
ICCD
2000
IEEE
13 years 9 months ago
2000
IEEE
In system-on-a-chip design, interfacing of Intellectual Property(IP) blocks is one of the most important issues. Since most IP’s are provided by different vendors, they have dif...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
ICCAD
2005
IEEE
13 years 10 months ago
2005
IEEE
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...