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TCAD
2008
92views more  TCAD 2008»
13 years 4 months ago
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar
ICCS
2007
Springer
13 years 9 months ago
Building Verifiable Sensing Applications Through Temporal Logic Specification
Abstract. Sensing is at the core of virtually every DDDAS application. Sensing applications typically involve distributed communication and coordination over large self-organized n...
Asad Awan, Ahmed H. Sameh, Suresh Jagannathan, Ana...
DAC
2003
ACM
14 years 6 months ago
The synthesis of cyclic combinational circuits
Combinational circuits are generally thought of as acyclic structures. It is known that cyclic structures can be combinational, and techniques have been proposed to analyze cyclic...
Marc D. Riedel, Jehoshua Bruck
DAC
2003
ACM
14 years 6 months ago
On-chip logic minimization
While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such a...
Roman L. Lysecky, Frank Vahid
ICCAD
2004
IEEE
111views Hardware» more  ICCAD 2004»
14 years 2 months ago
A new incremental placement algorithm and its application to congestion-aware divisor extraction
— This paper presents two contributions. The first is an incremental placement algorithm for placement-aware logic synthesis along with a proof of optimality. The algorithm can ...
Satrajit Chatterjee, Robert K. Brayton