19 search results - page 1 / 4 » Synthesis for Logical Initializability of Synchronous Finite... |
VLSID
1997
IEEE
13 years 9 months ago
1997
IEEE
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
ISCAS
2002
IEEE
13 years 10 months ago
2002
IEEE
A technique for computing the switching activity of synchronous Finite State Machine (FSM) implementations including the influence of temporal correlation among the next state si...
ITC
1999
IEEE
13 years 9 months ago
1999
IEEE
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
FPL
2000
Springer
13 years 9 months ago
2000
Springer
This paper discusses the design and implementation of finite state machines (FSM) with combinational circuits that are built primarily from RAM blocks. It suggests a novel state as...