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» Synthesis of Efficient Linear Test Pattern Generators
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VTS
1999
IEEE
106views Hardware» more  VTS 1999»
13 years 9 months ago
RT-level TPG Exploiting High-Level Synthesis Information
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
ITC
1998
IEEE
114views Hardware» more  ITC 1998»
13 years 9 months ago
BETSY: synthesizing circuits for a specified BIST environment
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
Zhe Zhao, Bahram Pouya, Nur A. Touba
GLVLSI
1997
IEEE
92views VLSI» more  GLVLSI 1997»
13 years 8 months ago
An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation
H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor V...
ICCAD
2002
IEEE
152views Hardware» more  ICCAD 2002»
14 years 1 months ago
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. A common approach used in the design of such instruc...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt
DELTA
2008
IEEE
13 years 11 months ago
AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis
Re-using embedded resources for implementing builtin self test mechanisms allows test cost reduction. In this paper we demonstrate how to implement costefficient built-in self tes...
M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre