9 search results - page 1 / 2 » Synthesis of synchronous assertions with guarded atomic acti... |
MEMOCODE
2005
IEEE
13 years 10 months ago
2005
IEEE
The SystemVerilog standard introduces SystemVerilog Assertions (SVA), a synchronous assertion package based on the temporal-logic semantics of PSL. Traditionally assertions are ch...
LCTRTS
2010
Springer
13 years 3 months ago
2010
Springer
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...
ICCAD
2005
IEEE
14 years 2 months ago
2005
IEEE
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...
DAC
2004
ACM
14 years 6 months ago
2004
ACM
A modular synthesis flow is essential for a scalable and hierarchical design methodology. This paper considers a particular modular flow where each module has interface methods an...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...