Sciweavers

10159 search results - page 2 / 2032
» System Design Validation Using Formal Models
Sort
View
UML
2005
Springer
13 years 11 months ago
Using Process Algebra to Validate Behavioral Aspects of Object-Oriented Models
We present in this paper a rigorous and automated based approach for the behavioral validation of control software systems. This approach relies on metamodeling, model-transformati...
Alban Rasse, Jean-Marc Perronne, Pierre-Alain Mull...
AOSE
2004
Springer
13 years 11 months ago
A Formal Approach to Design and Reuse Agent and Multiagent Models
While there are many useful models of agents and multi-agent systems, they are typically defined in an informal way and applied in an ad-hoc fashion. Consequently, multi-agent sys...
Vincent Hilaire, Olivier Simonin, Abder Koukam, Ja...
CODES
2004
IEEE
13 years 9 months ago
System-on-chip validation using UML and CWL
In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design...
Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo...
HASE
2008
IEEE
13 years 5 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri
SEW
2006
IEEE
13 years 11 months ago
Retrenching the Purse: Finite Exception Logs, and Validating the Small
The Mondex Electronic Purse is an outstanding example of industrial scale formal refinement, and was the first verification to achieve ITSEC level E6 certification. A formal a...
Richard Banach, Michael Poppleton, Susan Stepney