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» System chip test: how will it impact your design
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ETS
2007
IEEE
91views Hardware» more  ETS 2007»
13 years 11 months ago
PPM Reduction on Embedded Memories in System on Chip
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests a...
Said Hamdioui, Zaid Al-Ars, Javier Jiménez,...
DAC
2002
ACM
14 years 6 months ago
The next chip challenge: effective methods for viable mixed technology SoCs
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...
H. Bernhard Pogge
TVLSI
2008
105views more  TVLSI 2008»
13 years 5 months ago
Robust Concurrent Online Testing of Network-on-Chip-Based SoCs
Lifetime concerns for complex systems-on-a-chip (SoC) designs due to decreasing levels in reliability motivate the development of solutions to ensure reliable operation. A precurso...
Praveen Bhojwani, Rabi N. Mahapatra
PATMOS
2000
Springer
13 years 9 months ago
Early Power Estimation for System-on-Chip Designs
Abstract. Reduction of chip packaging and cooling costs for deep sub-micron SystemOn-Chip (SOC) designs is an emerging issue. We present a simulation-based methodology able to real...
Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reo...
UML
2001
Springer
13 years 9 months ago
Agile Modeling: A Brief Overview
: Agile Modeling (AM) is a practice-based methodology for effective modeling of software-based systems. Where the Unified Modeling Language (UML) defines a subset of the modeling t...
Scott W. Ambler