93 search results - page 1 / 19 » System-level memory modeling for bus-based memory architectu... |
TC
2010
12 years 11 months ago
2010
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
ISSS
1997
IEEE
13 years 8 months ago
1997
IEEE
In this paper, our memory architecture exploration methodology and CAD techniques for network protocol applications are presented. Prototype tools have been implemented, and appli...
EUROPAR
1997
Springer
13 years 8 months ago
1997
Springer
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to ...
CODES
2006
IEEE
13 years 10 months ago
2006
IEEE
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
— It is predicted that 70% of the chip area will be occupied by memories in future system-onchips. The minimization of on-chip memory hence becomes increasingly important for cos...