17 search results - page 1 / 4 » System-level performance optimization of the data queueing m... |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
: - One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at...
HOTI
2005
IEEE
13 years 10 months ago
2005
IEEE
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
ISCA
1996
IEEE
13 years 9 months ago
1996
IEEE
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
CANPC
1998
Springer
13 years 9 months ago
1998
Springer
Abstract. Modern networks of workstations connected by Gigabit networks have the ability to run high-performance computing applications at a reasonable performance, but at a signi ...