74 search results - page 1 / 15 » TELIOS: A Tool for the Automatic Generation of Logic Program... |
IFIP12
2009
13 years 2 months ago
2009
In this paper the tool TELIOS is presented, for the automatic generation of a hardware machine, corresponding to a given logic program. The machine is implemented using an FPGA, wh...
CADE
2008
Springer
14 years 5 months ago
2008
Springer
We present a tool for automatic generation of packed bitfields and tagged unions for systems-level C, along with automatic, machine checked refinement proofs in Isabelle/HOL. Our a...
FLOPS
2010
Springer
13 years 11 months ago
2010
Springer
We present a general framework for generating SQL query test cases using Constraint Logic Programming. Given a database schema and a SQL view defined in terms of other views and s...
CHI
2010
ACM
13 years 10 months ago
2010
ACM
Paper prototyping offers unique affordances for interface design. However, due to its spontaneous nature and the limitations of paper, it is difficult to distill and communicate a...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...