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ISCAS
2003
IEEE
77views Hardware» more  ISCAS 2003»
13 years 10 months ago
Table look-up based compact modeling for on-chip interconnect timing and noise analysis
Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushi...
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
13 years 9 months ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli
DAC
2008
ACM
14 years 5 months ago
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
S. Raja, F. Varadi, Murat R. Becer, Joao Geada