30 search results - page 6 / 6 » Tableaux and Model Checking for Memory Logics |
TACAS
1998
Springer
13 years 9 months ago
1998
Springer
In this paper, we report on an application of the validation and veri cation tool kit Uppaal in the design and analysis of a prototype gear controller, carried out in a joint proje...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
CAV
1998
Springer
13 years 9 months ago
1998
Springer
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
DATE
2009
IEEE
14 years 2 days ago
2009
IEEE
Abstract—Addressing both standby and active power is a major challenge in developing System-on-Chip designs for batterypowered products. Powering off sections of logic or memorie...
PLDI
2010
ACM
13 years 10 months ago
2010
ACM
Many opportunities for easy, big-win, program optimizations are missed by compilers. This is especially true in highly layered Java applications. Often at the heart of these misse...