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» Tag Overflow Buffering: An Energy-Efficient Cache Architectu...
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DATE
2005
IEEE
84views Hardware» more  DATE 2005»
13 years 11 months ago
Tag Overflow Buffering: An Energy-Efficient Cache Architecture
Mirko Loghi, Paolo Azzoni, Massimo Poncino
ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
13 years 3 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
WMPI
2004
ACM
13 years 10 months ago
Addressing mode driven low power data caches for embedded processors
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
Ramesh V. Peri, John Fernando, Ravi Kolagotla
MOBIHOC
2008
ACM
14 years 4 months ago
Rendezvous design algorithms for wireless sensor networks with a mobile base station
Recent research shows that significant energy saving can be achieved in wireless sensor networks with a mobile base station that collects data from sensor nodes via short-range co...
Guoliang Xing, Tian Wang, Weijia Jia, Minming Li
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 3 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...