83 search results - page 1 / 17 » Technology Mapping for Reliability Enhancement in Logic Synt... |
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
DAC
2010
ACM
13 years 8 months ago
2010
ACM
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to th...
DSN
2009
IEEE
2009
IEEE
Processor reliability enhancement through compiler-directed register file peak temperature reduction
13 years 8 months ago
Each semiconductor technology generation brings us closer to the imminent processor architecture heat wall, with all its associated adverse effects on system performance and reliab...