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» Technology mapping and packing for coarse-grained, anti-fuse...
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ASPDAC
2004
ACM
81views Hardware» more  ASPDAC 2004»
13 years 10 months ago
Technology mapping and packing for coarse-grained, anti-fuse based FPGAs
Chang Woo Kang, Ali Iranli, Massoud Pedram
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 2 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He