18 search results - page 1 / 4 » Temperature-Sensitive Loop Parallelization for Chip Multipro... |
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to re...
CJ
2006
13 years 4 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
ICPADS
2006
IEEE
13 years 10 months ago
2006
IEEE
One of the major factors that can potentially slow down widespread use of embedded chip multiprocessors is lack of efficient software support. In particular, automated code paral...
CASES
2009
ACM
13 years 11 months ago
2009
ACM
This paper solves the open problem of extracting the maximal number of iterations from a loop that can be executed in parallel on chip multiprocessors. Our algorithm solves it opt...
EMSOFT
2005
Springer
13 years 10 months ago
2005
Springer
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...