Temperature-Sensitive Loop Parallelization for Chip Multiprocessors

In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9◦ C (4.3◦ C) when averaged over all the applications tested, incurring small performance/power penalties.

• Type: Conference
• Year: 2005
• Where: ICCD
• Authors: Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T. Kandemir, Yuan Xie
• Keywords: Chip Multiprocessors, Hardware, ICCD 2005, Peak Temperature, Temperature-sensitive Loop Parallelization