1016 search results - page 1 / 204 » Test Generation for Designs with On-Chip Clock Generators |
ATS
2009
IEEE
13 years 11 months ago
2009
IEEE
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
MSE
2003
IEEE
13 years 10 months ago
2003
IEEE
A tool has been developed to automate the testing and grading of design projects implemented in reprogrammable hardware. The server allows multiple students to test circuits in FP...
ETS
2006
IEEE
13 years 11 months ago
2006
IEEE
A central problem in built-in self test (BIST) is how to efficiently generate a small set of test vectors that detect all targeted faults. We propose a novel solution that uses l...