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» Test Strategies for Low Power Devices
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DATE
2008
IEEE
111views Hardware» more  DATE 2008»
13 years 11 months ago
Power-Aware Testing and Test Strategies for Low Power Devices
Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, ...
DATE
2008
IEEE
123views Hardware» more  DATE 2008»
13 years 11 months ago
Test Strategies for Low Power Devices
Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing...
C. P. Ravikumar, M. Hirech, X. Wen
ETS
2007
IEEE
128views Hardware» more  ETS 2007»
13 years 6 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....
DAC
2005
ACM
14 years 5 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer
ISQED
2000
IEEE
131views Hardware» more  ISQED 2000»
13 years 9 months ago
Low Power Testing of VLSI Circuits: Problems and Solutions
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
Patrick Girard