248 search results - page 4 / 50 » Test exploration and validation using transaction level mode... |
MTV
2005
IEEE
13 years 10 months ago
2005
IEEE
The increasing complexity and size of system level design models introduces a difficult challenge for validating them. Hence, in most industries, design validation takes a large p...
DSD
2004
IEEE
13 years 9 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
CODES
2003
IEEE
13 years 10 months ago
2003
IEEE
the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impa...
LCTRTS
2007
Springer
13 years 11 months ago
2007
Springer
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
HIPC
2009
Springer
13 years 3 months ago
2009
Springer
Software transactional memory (STM) is an emerging concurrency control mechanism for shared memory accesses. Early abort is one of the important techniques to improve the executio...