321 search results - page 1 / 65 » Test scheduling for core-based systems |
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
This paper proposes a comprehensive model for test planning in a core-based environment. The main contribution of this work is the use of several types of TAMs and the considerati...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
DAC
1998
ACM
14 years 6 months ago
1998
ACM
The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by domin...
DSD
2009
IEEE
13 years 11 months ago
2009
IEEE
—Long test application time and high temperature have become two major issues of system-on-chip (SoC) test. In order to minimize test application times and avoid overheating duri...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...