27 search results - page 1 / 6 » The Design and Evaluation of Policy-Controllable Buffer Cach... |
ICPADS
1997
IEEE
13 years 9 months ago
1997
IEEE
ISCA
1997
IEEE
13 years 9 months ago
1997
IEEE
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
EUROSYS
2011
ACM
12 years 8 months ago
2011
ACM
Buffer caches in operating systems keep active file blocks in memory to reduce disk accesses. Related studies have been focused on how to minimize buffer misses and the caused pe...
ISCA
1994
IEEE
13 years 9 months ago
1994
IEEE
Today's commodity microprocessors require a low latency memory system to achieve high sustained performance. The conventional high-performance memory system provides fast dat...
ICCD
1999
IEEE
13 years 9 months ago
1999
IEEE
This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compresse...