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» The Design of Residue Number System Arithmetic Units for A V...
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CASES
2009
ACM
13 years 8 months ago
Exploiting residue number system for power-efficient digital signal processing in embedded processors
2's complement number system imposes a fundamental limitation on the power and performance of arithmetic circuits, due to the fundamental need of cross-datapath carry propaga...
Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shr...
FCCM
2007
IEEE
107views VLSI» more  FCCM 2007»
13 years 11 months ago
Optimizing Logarithmic Arithmetic on FPGAs
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, ...
Haohuan Fu, Oskar Mencer, Wayne Luk
APCSAC
2003
IEEE
13 years 10 months ago
Arithmetic Circuits Combining Residue and Signed-Digit Representations
This paper discusses the use of signed-digit representations in the implementation of fast and efficient residue-arithmetic units. Improvements to existing signed-digit modulo adde...
Anders Lindström, Michael Nordseth, Lars Beng...
ISLPED
1995
ACM
113views Hardware» more  ISLPED 1995»
13 years 8 months ago
Low delay-power product CMOS design using one-hot residue coding
: CMOS implementations of arithmetic units for One-Hot Residue encoded operands are presented. They are shown to reduce the delay-power product of conventional, fully-encoded desig...
William A. Chren Jr.