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» The Filter Cache: An Energy Efficient Memory Structure
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ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
13 years 11 months ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
GLOBECOM
2007
IEEE
13 years 12 months ago
Power Efficient IP Lookup with Supernode Caching
— In this paper, we propose a novel supernode caching scheme to reduce IP lookup latencies and energy consumption in network processors. In stead of using an expensive TCAM based...
Lu Peng, Wencheng Lu, Lide Duan
CAL
2008
13 years 5 months ago
Hierarchical Instruction Register Organization
This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient Filter Cache as a baseline and ...
David Black-Schaffer, James D. Balfour, William J....
HIPEAC
2010
Springer
13 years 3 months ago
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems
We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a ...
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iri...
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
13 years 10 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell