91 search results - page 3 / 19 » The High Road to Formal Validation: |
FDL
2008
IEEE
13 years 7 months ago
2008
IEEE
This paper describes a scenario-based methodology em-level design validation based on the Abstract State Machines formal method. This scenario-based approach complements an existi...
COMPSAC
2009
IEEE
13 years 12 months ago
2009
IEEE
As computing technology becomes increasingly pervasive and interconnected, mobility leads to shorter-lasting relationships between end-points with many different security requirem...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
FMCAD
2009
Springer
13 years 11 months ago
2009
Springer
Abstract—Symbolic Trajectory Evaluation is an industrialstrength verification method, based on symbolic simulation and abstraction, that has been highly successful in data path ...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...