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» The High Road to Formal Validation:
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FDL
2007
IEEE
13 years 12 months ago
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
Lun Li, Frank P. Coyle, Mitchell A. Thornton
JCP
2008
116views more  JCP 2008»
13 years 5 months ago
Formal Verification and Visualization of Security Policies
Verified and validated security policies are essential components of high assurance computer systems. The design and implementation of security policies are fundamental processes i...
Luay A. Wahsheh, Daniel Conte de Leon, Jim Alves-F...
CCS
2004
ACM
13 years 11 months ago
Lessons learned using alloy to formally specify MLS-PCA trusted security architecture
In order to solve future Multi Level Security (MLS) problems, we have developed a solution based on the DARPA Polymorphous Computing Architecture (PCA). MLS-PCA uses a novel distr...
Brant Hashii
COMCOM
2000
130views more  COMCOM 2000»
13 years 5 months ago
Use Case Maps and LOTOS for the prototyping and validation of a mobile group call system
ABSTRACT -- SPEC-VALUE, a rigorous scenario-driven approach for the description and validation of complex system functionalities at the early stages of design, is presented. It is ...
Daniel Amyot, Luigi Logrippo
SOSE
2008
IEEE
14 years 22 hour ago
Precise Steps for Choreography Modeling for SOA Validation and Verification
Service-oriented architecture (SOA) enables organizations to transform their existing IT infrastructure into a more flexible business process platform.. In this architecture, deco...
Sebastian Wieczorek, Andreas Roth, Alin Stefanescu...