13 search results - page 3 / 3 » The LCD interconnection of LRU caches and its analysis |
SPAA
1996
ACM
13 years 9 months ago
1996
ACM
In this paper, we analyze the performance of parallel multithreaded algorithms that use dag-consistent distributed shared memory. Specifically, we analyze execution time, page fau...
CF
2004
ACM
13 years 10 months ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
ICPP
1993
IEEE
13 years 9 months ago
1993
IEEE
Scalability of parallel architectures is an interesting area of current research. Shared memory parallel programming is attractive stemming from its relative ease in transitioning...