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MICRO
1997
IEEE
105views Hardware» more  MICRO 1997»
13 years 9 months ago
The Multicluster Architecture: Reducing Cycle Time Through Partitioning
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of t...
Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvon...
VLSID
2002
IEEE
119views VLSI» more  VLSID 2002»
14 years 5 months ago
Reducing Library Development Cycle Time through an Optimum Layout Create Flow
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
Rituparna Mandal, Dibyendu Goswami, Arup Dash
ISPA
2004
Springer
13 years 10 months ago
Performance-Aware Load Balancing for Multiclusters
In a multicluster architecture, where jobs can be submitted through each constituent cluster, the job arrival rates in individual clusters may be uneven and the load therefore need...
Ligang He, Stephen A. Jarvis, David A. Bacigalupo,...
IEEEPACT
2003
IEEE
13 years 10 months ago
Reducing Datapath Energy through the Isolation of Short-Lived Operands
We present a technique for reducing the power dissipation in the course of writebacks and committments in a datapath that uses a dedicated architectural register file (ARF) to hol...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...
JSA
2006
67views more  JSA 2006»
13 years 4 months ago
Speedup of NULL convention digital circuits using NULL cycle reduction
A NULL Cycle Reduction (NCR) technique is developed to increase the throughput of NULL Convention Logic systems, by reducing the time required to flush complete DATA wavefronts, c...
S. C. Smith