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» The Optimum Pipeline Depth for a Microprocessor
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ISCA
2002
IEEE
127views Hardware» more  ISCA 2002»
13 years 9 months ago
The Optimum Pipeline Depth for a Microprocessor
The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing ar...
Allan Hartstein, Thomas R. Puzak
MICRO
2003
IEEE
124views Hardware» more  MICRO 2003»
13 years 10 months ago
Optimum Power/Performance Pipeline Depth
The impact of pipeline length on both the power and performance of a microprocessor is explored both theoretically and by simulation. A theory is presented for a wide range of pow...
Allan Hartstein, Thomas R. Puzak
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
13 years 9 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
IEEEPACT
2007
IEEE
13 years 11 months ago
Verification-Aware Microprocessor Design
The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. Howe...
Anita Lungu, Daniel J. Sorin
SAMOS
2005
Springer
13 years 10 months ago
Micro-architecture Performance Estimation by Formula
An analytical performance model for out of order issue superscalar micro-processors is presented. This model quantifies the performance impacts of micro-architecture design option...
Lucanus J. Simonson, Lei He