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ASPDAC
2006
ACM
143views Hardware» more  ASPDAC 2006»
13 years 11 months ago
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model
Abstract— Routing tree construction is a fundamental problem in modern VLSI design. In this paper we propose CDCTree, an Obstacle-Avoiding Rectilinear Steiner Minimum Tree (OARSM...
Yiyu Shi, Tong Jing, Lei He, Zhe Feng 0002, Xianlo...
VLSID
2002
IEEE
109views VLSI» more  VLSID 2002»
14 years 5 months ago
Probabilistic Analysis of Rectilinear Steiner Trees
Steiner tree is a fundamental problem in the automatic interconnect optimization for VLSI design. We present a probabilistic analysis method for constructing rectilinear Steiner t...
Chunhong Chen
WADS
2007
Springer
165views Algorithms» more  WADS 2007»
13 years 11 months ago
A Near Linear Time Approximation Scheme for Steiner Tree Among Obstacles in the Plane
We present a polynomial-time approximation scheme (PTAS) for the Steiner tree problem with polygonal obstacles in the plane with running time O(n log2 n), where n denotes the numb...
Matthias Müller-Hannemann, Siamak Tazari
SODA
2003
ACM
133views Algorithms» more  SODA 2003»
13 years 6 months ago
Integrality ratio for group Steiner trees and directed steiner trees
The natural relaxation for the Group Steiner Tree problem, as well as for its generalization, the Directed Steiner Tree problem, is a flow-based linear programming relaxation. We...
Eran Halperin, Guy Kortsarz, Robert Krauthgamer, A...
DAC
1994
ACM
13 years 9 months ago
Rectilinear Steiner Trees with Minimum Elmore Delay
We provide a new theoretical framework for constructing Steiner routing trees with minimum Elmore delay. Earlier work [3, 13] has established Elmore delay as a high delity estima...
Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCo...