48 search results - page 10 / 10 » The Validity of Retiming Sequential Circuits |
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniq...
ICCAD
2007
IEEE
13 years 9 months ago
2007
IEEE
Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for...
CF
2004
ACM
13 years 11 months ago
2004
ACM
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...