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CEC
2005
IEEE
13 years 11 months ago
FPGA segmented channel routing using genetic algorithms
A genetic algorithm approach for segmented channel routing in field programmable gate arrays (FPGA's) is presented in this paper. The FPGA segmented channel routing problem (F...
Lipo Wang, Lei Zhou, Wen Liu
GECCO
2004
Springer
182views Optimization» more  GECCO 2004»
13 years 10 months ago
On the Evolution of Analog Electronic Circuits Using Building Blocks on a CMOS FPTA
This article summarizes two experiments utilizing building blocks to find analog electronic circuits on a CMOS Field Programmable Transistor Array (FPTA). The FPTA features 256 pr...
Jörg Langeheine, Martin Trefzer, Daniel Br&uu...
CSREAESA
2010
13 years 3 months ago
The First Clock Cycle Is A Real BIST
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
Charles E. Stroud, Bradley F. Dutton
ANCS
2005
ACM
13 years 10 months ago
A novel reconfigurable hardware architecture for IP address lookup
IP address lookup is one of the most challenging problems of Internet routers. In this paper, an IP lookup rate of 263 Mlps (Million lookups per second) is achieved using a novel ...
Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabae...
ERSA
2006
113views Hardware» more  ERSA 2006»
13 years 6 months ago
A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead
Thermal monitoring of a design plays a vital role to ensure safe and reliable thermal operating conditions. Thermal monitoring by employing thermal sensors is a popular technique ...
Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci...