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» The deep sub-micron signal integrity challenge
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DAC
1999
ACM
14 years 5 months ago
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminate...
Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton,...
ICCAD
2006
IEEE
99views Hardware» more  ICCAD 2006»
14 years 1 months ago
Information theoretic approach to address delay and reliability in long on-chip interconnects
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
DSD
2002
IEEE
96views Hardware» more  DSD 2002»
13 years 9 months ago
Networks on Silicon: Blessing or Nightmare?
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Paul Wielage, Kees G. W. Goossens
GLVLSI
2006
IEEE
105views VLSI» more  GLVLSI 2006»
13 years 11 months ago
A practical approach for monitoring analog circuits
Formal methods have been advocated for the verification of digital design where correctness is proved mathematically. In contrast to digital designs, the verification of analog ...
Mohamed H. Zaki, Sofiène Tahar, Guy Bois