55 search results - page 3 / 11 » The design and implementation of a low-latency on-chip netwo... |
NSDI
2004
13 years 7 months ago
2004
Designing a wide-area distributed hash table (DHT) that provides high-throughput and low-latency network storage is a challenge. Existing systems have explored a range of solution...
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
ASAP
2003
IEEE
13 years 11 months ago
2003
IEEE
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
ISCAS
2006
IEEE
14 years 20 hour ago
2006
IEEE
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
Current Systems-On-Chip (SoC) execute applications that demand extensive parallel processing. Networks-OnChip (NoC) provide a structured way of realizing interconnections on silic...