Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverag...
Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Fo...
In this paper we show how an interactive system can be distributed among several peer devices. By taking advantage of the current trend towards ambient intelligent environments, w...
In a previous paper [BMR01], the authors showed that the mechanism underlying Logic Programming can be extended to handle the situation where the atoms are interpreted as subsets o...
Howard A. Blair, Victor W. Marek, Jeffrey B. Remme...
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...