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» The semantics of power and ARM multiprocessor machine code
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TACAS
2007
Springer
105views Algorithms» more  TACAS 2007»
13 years 11 months ago
Hoare Logic for Realistically Modelled Machine Code
This paper presents a mechanised Hoare-style programming logic framework for assembly level programs. The framework has been designed to fit on top of operational semantics of rea...
Magnus O. Myreen, Michael J. C. Gordon
DIMVA
2010
13 years 5 months ago
dAnubis - Dynamic Device Driver Analysis Based on Virtual Machine Introspection
Abstract. In the escalating arms race between malicious code and security tools designed to analyze it, detect it or mitigate its impact, malicious code running inside the operatin...
Matthias Neugschwandtner, Christian Platzer, Paolo...
LCTRTS
2000
Springer
13 years 8 months ago
Automatic Validation of Code-Improving Transformations
This paper presents a general approach to automatically validate code-improving transformations on low-level program representations. The approach ensures the correctness of compi...
Robert van Engelen, David B. Whalley, Xin Yuan
IJPP
2006
82views more  IJPP 2006»
13 years 5 months ago
Supporting Microthread Scheduling and Synchronisation in CMPs
Chip multiprocessors hold great promise for achieving scalability in future systems. Microthreaded chip multiprocessors add a means of exploiting legacy code in such systems. Usin...
Ian Bell, Nabil Hasasneh, Chris R. Jesshope
CODES
2008
IEEE
13 years 11 months ago
Distributed and low-power synchronization architecture for embedded multiprocessors
In this paper we present a framework for a distributed and very low-cost implementation of synchronization controllers and protocols for embedded multiprocessors. The proposed arc...
Chenjie Yu, Peter Petrov