48 search results - page 4 / 10 » The synthesis of combinational logic to generate probabiliti... |
ISLPED
1995
ACM
13 years 9 months ago
1995
ACM
We present a technique that automatically synthesizes nite state machines with gated clocks to reduce the power dissipation of the nal implementation. We describe a new transfor...
DAC
2002
ACM
14 years 7 months ago
2002
ACM
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) -- representation...
MEMOCODE
2007
IEEE
14 years 8 days ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
ICCAD
1996
IEEE
13 years 10 months ago
1996
IEEE
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with ...