66 search results - page 2 / 14 » Thread Cluster Memory Scheduling: Exploiting Differences in ... |
IPPS
2009
IEEE
13 years 11 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
HPCA
2007
IEEE
14 years 5 months ago
2007
IEEE
Utilizing the nonuniform latencies of SDRAM devices, access reordering mechanisms alter the sequence of main memory access streams to reduce the observed access latency. Using a r...
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
SAC
2008
ACM
13 years 4 months ago
2008
ACM
In this work we modify the conventional row buffer allocation mechanism used in DDR2 SDRAM banks to improve average memory latency and overall processor performance. Our method as...
HOTOS
2009
IEEE
13 years 8 months ago
2009
IEEE
High performance on multicore processors requires that schedulers be reinvented. Traditional schedulers focus on keeping execution units busy by assigning each core a thread to ru...