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2008
ACM

Exploiting program cyclic behavior to reduce memory latency in embedded processors

10 years 9 months ago
Exploiting program cyclic behavior to reduce memory latency in embedded processors
In this work we modify the conventional row buffer allocation mechanism used in DDR2 SDRAM banks to improve average memory latency and overall processor performance. Our method assigns row buffers to different banks dynamically and by taking into account program cyclic behavior and bank row buffer demand. As we show in this work, memory requests go through several phases. In each phase, programs tend to access a single bank most of the time. We exploit this repetitive behavior and improve the concurrency level for memory read and write operations. We do so by assigning idle row buffers to more demanding banks during specific program phases. This improves average memory latency and processor performance by 12.7% and 7.6% respectively. Categories and Subject Descriptors
Ehsan Atoofian, Amirali Baniasadi
Added 28 Dec 2010
Updated 28 Dec 2010
Type Journal
Year 2008
Where SAC
Authors Ehsan Atoofian, Amirali Baniasadi
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