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EUROPAR
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
HICSS
1995
IEEE
13 years 8 months ago
1995
IEEE
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...