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» Tiling Imperfectly-Nested Loop Nests
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ICS
2009
Tsinghua U.
13 years 11 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
SC
2000
ACM
13 years 9 months ago
Tiling Imperfectly-Nested Loop Nests
Nawaaz Ahmed, Nikolay Mateev, Keshav Pingali
ICS
1999
Tsinghua U.
13 years 9 months ago
An experimental evaluation of tiling and shackling for memory hierarchy management
On modern computers, the performance of programs is often limited by memory latency rather than by processor cycle time. To reduce the impact of memory latency, the restructuring ...
Induprakas Kodukula, Keshav Pingali, Robert Cox, D...
IPPS
2010
IEEE
13 years 2 months ago
DynTile: Parametric tiled loop generation for parallel execution on multicore processors
Abstract--Loop tiling is an important compiler transformation used for enhancing data locality and exploiting coarsegrained parallelism. Tiled codes in which tile sizes are runtime...
Albert Hartono, Muthu Manikandan Baskaran, J. Rama...
HIPS
1998
IEEE
13 years 9 months ago
Further Results for Improving Loop Interchange in Non-Adjacent and Imperfectly Nested Loops
Loop interchange is a powerful restructuring technique for supporting vectorization and parallelization. In this paper, we propose a technique which is better to determine whether...
Tsung-Chuan Huang, Cheng-Ming Yang