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» Tiling Imperfectly-Nested Loop Nests
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ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
13 years 3 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
JISE
1998
84views more  JISE 1998»
13 years 5 months ago
Determining the Idle Time of a Tiling: New Results
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. We build upon recent results by ...
Frederic Desprez, Jack Dongarra, Fabrice Rastello,...
ASAP
1997
IEEE
107views Hardware» more  ASAP 1997»
13 years 9 months ago
Tiling with limited resources
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. Little work has been devoted to ...
Pierre-Yves Calland, Jack Dongarra, Yves Robert
CC
2008
Springer
193views System Software» more  CC 2008»
13 years 7 months ago
Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model
The polyhedral model provides powerful abstractions to optimize loop nests with regular accesses. Affine transformations in this model capture a complex sequence of execution-reord...
Uday Bondhugula, Muthu Manikandan Baskaran, Sriram...
IEEEPACT
2009
IEEE
14 years 12 days ago
Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
Basilio B. Fraguela, Yevgen Voronenko, Markus P&uu...