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1997
IEEE

Tiling with limited resources

9 years 6 months ago
Tiling with limited resources
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. Little work has been devoted to the mapping and scheduling of the tiles on to physical processors. We present several new results in the context of limited computational resources, and assuming communication-computation overlap. In particular, under some reasonable assumptions, we derive the optimal mapping and scheduling of tiles to physical processors. Cover Page Information Corresponding author: Yves Robert Submitted as: Regular paper Conference area: Design methodologies, Compilers This work was supported in part by the National Science Foundation Grant No. ASC-9005933; by the Defense Advanced Research Projects Agency under contract DAAH04-95-1-0077, administered by the Army Research O ce; by the O ce of Scienti c Computing, U.S. Department of Energy, under Contract DE-AC05-84OR21400; by the National Science Foundation Science and Tech...
Pierre-Yves Calland, Jack Dongarra, Yves Robert
Added 25 Aug 2010
Updated 25 Aug 2010
Type Conference
Year 1997
Where ASAP
Authors Pierre-Yves Calland, Jack Dongarra, Yves Robert
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