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» Time-constrained code compaction for DSPs
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ISSS
1995
IEEE
96views Hardware» more  ISSS 1995»
13 years 8 months ago
Time-constrained code compaction for DSPs
{DSP algorithms in most cases are subject to hard real-time constraints. In case of programmable DSP processors, meeting those constraints must be ensured by appropriate code gener...
Rainer Leupers, Peter Marwedel
DATE
2004
IEEE
122views Hardware» more  DATE 2004»
13 years 8 months ago
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm
The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular arc...
Markus Lorenz, Peter Marwedel
ICESS
2007
Springer
13 years 11 months ago
Memory Offset Assignment for DSPs
Compact code generation is very important for an embedded system that has to be implemented on a chip with a severely limited amount of size. Even though on-chip data memory optimi...
Jinpyo Hong, J. Ramanujam
LCTRTS
2001
Springer
13 years 9 months ago
A Dynamic Programming Approach to Optimal Integrated Code Generation
Phase-decoupled methods for code generation are the state of the art in compilers for standard processors but generally produce code of poor quality for irregular target architect...
Christoph W. Keßler, Andrzej Bednarski