40 search results - page 2 / 8 » Timing Driven Placement for Large Standard Cell Circuits |
ISPD
1997
ACM
13 years 9 months ago
1997
ACM
In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations. As netlist transformations a...
GECCO
2004
Springer
13 years 10 months ago
2004
Springer
Genetic algorithms require relatively large computation time to solve optimization problems, especially in VLSI CAD such as module placement. Therefore, island-based parallel GAs a...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...
FPGA
1998
ACM
13 years 9 months ago
1998
ACM
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
− In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed th...