72 search results - page 1 / 15 » Timing Optimization of Logic Network Using Gate Duplication |
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication...
ICCAD
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper addresses the issue of timing driven gate duplication for delay optimization. Gate duplication has been used extensively for cutset minimization but the usefulness in m...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
ICCAD
2008
IEEE
13 years 11 months ago
2008
IEEE
— To save power consumption, it has been shown that the clock signal can be gated without changing the functionality under certain clock-gating conditions. We observe that the cl...
VLSID
1999
IEEE
13 years 9 months ago
1999
IEEE
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach mak...