72 search results - page 3 / 15 » Timing Optimization of Logic Network Using Gate Duplication |
GECCO
2008
Springer
13 years 7 months ago
2008
Springer
For artificial entities to achieve high degrees of autonomy they will need to display appropriate adaptability. In this sense adaptability includes representational flexibility gu...
DSD
2007
IEEE
14 years 16 days ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
GECCO
2005
Springer
2005
Springer
Providing information from the environment for growing electronic circuits through polymorphic gates
13 years 11 months ago
This paper deals with the evolutionary design of programs (constructors) that are able to create (n+2)-input circuits from n-input circuits. The growing circuits are composed of p...
GECCO
2009
Springer
14 years 23 days ago
2009
Springer
VLSI research, in its continuous push toward further miniaturisation, is seeking to break through the limitations of current circuit manufacture techniques by moving towards biomi...
EUROGP
2000
Springer
13 years 9 months ago
2000
Springer
1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in rst time. The new representation of logic...